Analysis and Experimental Results of Interior DAC of SAR ADC using Cadence
نویسندگان
چکیده
Abstract: This paper focuses on analysis and experimental results of 6-bit charge-redistribution DAC and 6-bit charge-redistribution DAC using split array configuration. These DAC configurations are designed and simulated using GPDK 180nm CMOS technology. DAC is an important component within the SAR ADC. The charge redistribution DAC in a Split capacitor configuration has a total capacitance which is 87.5% smaller compared to a conventional design. Hence DAC gives the optimized architecture. Optimized design of DAC architecture ensures the accuracy of the components, which improves the performance of SAR ADC. The matching accuracy of integrated capacitors is excellent. The simulation results of both are compared. The delay required to get the output is 793.7E-15S and 793.6E-15S when all input bits are high for charge-redistribution DAC and split array DAC respectively. Dynamic range for these DACs is 35.98dB. The supply voltage is 1.8V.
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Design and Optimization on the Interior DAC of SAR ADC
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